Technical Field
The present invention relates to safely reducing wasted energy and, more particularly, to safely optimizing chip operating voltage.
Description of the Related Art
Integrated circuit components generally need a certain voltage level to operate correctly and safely. However, due to process, voltage, and temperature variations, this threshold voltage can change from chip to chip and even from component to component within a single chip. As such, traditional processor design uses a static voltage guardband to ensure safe operation.
However, the static guardband approach wastes energy because the guardband is selected to accommodate the worst case circumstances—a rare event. There are a variety of solutions to this problem in the art. In a first solution, the operating voltage is dynamically adjusted to overcome variations by detecting the available timing margin with a critical path monitor. In a second solution, the clock cycle is adaptively tuned according to a supply voltage value. In a third solution, an on-die power supply monitor circuit is used to monitor voltage droop events and increase the clock cycle upon detecting a voltage droop. In fourth solution, a tunable replica circuit at the root of clock distribution is used to detect the available timing margin and to adjust the voltage dynamically. In a fifth solution, a program signature and microarchitectural events are used to predict a large voltage droop.
However, all of these solutions reactively adjust the voltage during program execution and many use specialized circuits.